Intel Server CPU v5.1.11
Intel Xeon Processor L5506
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | Intel Xeon Processor L5506 |
| Processor number | L5506 |
| Codename | Nehalem EP |
| Generation | Nehalem |
| Microarchitecture | Nehalem |
| Performance class | Xeon 5000 series |
| Segment | Server |
| Released | 2009-Q12009 |
| Status | Discontinued |
| Cores | 4 |
| Threads | 4 |
| Base clock | 2.13 GHz |
| Cache | 4 MB Intel Smart Cache |
| Bus | 4.8 GT/s |
| TDP | 60 W |
| Lithography (as published) | 45 nm |
| Max memory | 144 GB |
| Memory channels | 3 |
| Max CPUs per system | 2 |
| Instruction set | 64-bit |
| Socket | FCLGA1366LGA1366 |
| Memory | DDR3 800DDR3 |
| Recommended price | $423 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v13.0.0(45 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.1(SSE4.2)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
- Foreshadow / L1 Terminal Fault (CVE-2018-3615, CVE-2018-3620, CVE-2018-3646): Speculative reads from the L1 data cache through non-present page table entries, breaking SGX, OS and VMM isolation.
- Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout) (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091): Data in store buffers, fill buffers and load ports leaks across privilege boundaries.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Server CPU v5.1.10 (Xeon EC5549)
Features
- +Physical Address Extension
- −Hyper-Threading
Specifications
- ~Codename: Jasper Forest → Nehalem EP
- ~Threads: 8 → 4
- ~Base clock: 2.53 GHz → 2.13 GHz
- ~Cache: 8 MB L3 Cache → 4 MB Intel Smart Cache
- ~Bus: 5.87 GT/s → 4.8 GT/s
- ~TDP: 85 W → 60 W
- +Max memory: 144 GB
- ~Recommended price: $503 → $423
- −Max clock: 2.93 GHz
- −PCIe revision: 2.0
Since the previous minor (lower performance class): Intel Server CPU v5.0.11 (Xeon X3430)
Breaking changes
- ~Socket changed from LGA1156 to FCLGA1366
Features
- −Trusted Execution Technology
Specifications
- ~Codename: Lynnfield → Nehalem EP
- ~Base clock: 2.40 GHz → 2.13 GHz
- ~Cache: 8 MB Intel Smart Cache → 4 MB Intel Smart Cache
- ~Bus: 2.5 GT/s → 4.8 GT/s
- ~TDP: 95 W → 60 W
- ~Max memory: 32 GB → 144 GB
- ~Memory channels: 2 → 3
- ~Max CPUs per system: 1 → 2
- ~Recommended price: $203 → $423
- −Max clock: 2.80 GHz
- −PCIe revision: 2.0
- −PCIe lanes: 16
- −Transistors: 774 million
- −Die size: 296 mm2
Since the previous major (previous generation): Intel Server CPU v4.1.11 (Xeon L5215)
Security
- !Introduced: Foreshadow / L1 Terminal Fault
- !Introduced: Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout)
Components
Instruction sets
- +SSE4.2
Features
- +VT-d
- +EPT
- +Physical Address Extension
- +ECC memory
- +Demand Based Switching
Specifications
- ~Codename: Wolfdale → Nehalem EP
- ~Microarchitecture: Penryn → Nehalem
- ~Cores: 2 → 4
- +Threads: 4
- ~Base clock: 1.86 GHz → 2.13 GHz
- ~Cache: 6 MB L2 Cache → 4 MB Intel Smart Cache
- ~Bus: 1066 MHz → 4.8 GT/s
- ~TDP: 20 W → 60 W
- +Max memory: 144 GB
- +Memory channels: 3
- +Max CPUs per system: 2
- +Recommended price: $423
- −Transistors: 410 million
- −Die size: 107 mm2
Raw source data
Show all 41 fields
| Field | Value |
|---|---|
| CpuId | 40712 |
| CpuName | Intel Xeon Processor L5506 |
| BornOnDate | Q1'09 |
| Bus | 4.8 GT/s |
| BusNumPorts | 2 |
| Cache | 4 MB Intel Smart Cache |
| ClockSpeed | 2.13 GHz |
| CodeNameText | Products formerly Nehalem EP |
| CoreCount | 4 |
| DemandBasedSwitching | Yes |
| ECCMemory | Yes |
| EM64 | Yes |
| Embedded | No |
| ExecuteDisable | Yes |
| ExtendedPageTables | Yes |
| HaltState | Yes |
| HyperThreading | No |
| InstructionSet | 64-bit |
| Lithography | 45 nm |
| MarketSegment | Server |
| MaxCPUs | 2 |
| MaxMem | 144 GB |
| MaxMemoryBandwidth | 19.2 GB/s |
| MaxTDP | 60 W |
| MemoryTypes | DDR3 800 |
| NumMemoryChannels | 3 |
| PackageSize | 42.5mm x 45mm |
| PhysicalAddressExtension | 40-bit |
| ProcessorNumber | L5506 |
| ProductGroup | Legacy Intel Xeon Processors |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | FCLGA1366 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| TBTVersion | No |
| TCase | 70°C |
| ThreadCount | 4 |
| TXT | No |
| VTD | Yes |
| VTX | Yes |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/40712/intel-xeon-processor-l5506-4m-cache-2-13-ghz-4-80-gts-intel-qpi.html |