Intel Server CPU v5.3.4
Intel Xeon Processor L7555
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | Intel Xeon Processor L7555 |
| Processor number | L7555 |
| Codename | Nehalem EX |
| Generation | Nehalem |
| Microarchitecture | Nehalem |
| Performance class | Xeon 7000 series |
| Segment | Server |
| Released | 2010-Q12010 |
| Status | Discontinued |
| Cores | 8 |
| Threads | 16 |
| Base clock | 1.87 GHz |
| Max clock | 2.53 GHz |
| Cache | 24 MB L3 Cache |
| Bus | 5.86 GT/s |
| TDP | 95 W |
| Lithography (as published) | 45 nm |
| Socket | FCLGA1567LGA1567 |
| Recommended price | $3,157 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v13.0.0(45 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.1(SSE4.2)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
- Foreshadow / L1 Terminal Fault (CVE-2018-3615, CVE-2018-3620, CVE-2018-3646): Speculative reads from the L1 data cache through non-present page table entries, breaking SGX, OS and VMM isolation.
- Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout) (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091): Data in store buffers, fill buffers and load ports leaks across privilege boundaries.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Server CPU v5.3.3 (Xeon L7545)
Specifications
- ~Cores: 6 → 8
- ~Threads: 12 → 16
- ~Cache: 18 MB L3 Cache → 24 MB L3 Cache
- ~Recommended price: $2,087 → $3,157
Since the previous minor (lower performance class): Intel Server CPU v5.2.2 (Xeon X6550)
Specifications
- ~Base clock: 2.00 GHz → 1.87 GHz
- ~Max clock: 2.40 GHz → 2.53 GHz
- ~Cache: 18 MB L3 Cache → 24 MB L3 Cache
- ~Bus: 6.4 GT/s → 5.86 GT/s
- ~TDP: 130 W → 95 W
- ~Recommended price: $2,461 → $3,157
Since the previous major (previous generation): Intel Server CPU v4.2.4 (Xeon L7445)
Breaking changes
- ~Socket changed from PGA604 to FCLGA1567
Security
- !Introduced: Foreshadow / L1 Terminal Fault
- !Introduced: Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout)
Components
Instruction sets
- +SSE4.2
Features
- +Hyper-Threading
- +EPT
- +Enhanced SpeedStep
- −Demand Based Switching
Specifications
- ~Codename: Dunnington → Nehalem EX
- ~Microarchitecture: Penryn → Nehalem
- ~Cores: 4 → 8
- +Threads: 16
- ~Base clock: 2.13 GHz → 1.87 GHz
- +Max clock: 2.53 GHz
- ~Cache: 12 MB L2 Cache → 24 MB L3 Cache
- ~Bus: 1066 MHz → 5.86 GT/s
- ~TDP: 50 W → 95 W
- ~Recommended price: $1,980 → $3,157
- −Transistors: 1900 million
- −Die size: 503 mm2
- −Instruction set: 64-bit
Raw source data
Show all 29 fields
| Field | Value |
|---|---|
| CpuId | 46494 |
| CpuName | Intel Xeon Processor L7555 |
| BornOnDate | Q1'10 |
| Bus | 5.86 GT/s |
| Cache | 24 MB L3 Cache |
| ClockSpeed | 1.87 GHz |
| ClockSpeedMax | 2.53 GHz |
| CodeNameText | Products formerly Nehalem EX |
| CoreCount | 8 |
| EM64 | Yes |
| Embedded | No |
| ExecuteDisable | Yes |
| ExpectedDiscontinuanceDate | Q4'2012 |
| ExtendedPageTables | Yes |
| HyperThreading | Yes |
| Lithography | 45 nm |
| MarketSegment | Server |
| MaxTDP | 95 W |
| ProcessorNumber | L7555 |
| ProductGroup | Legacy Intel Xeon Processors |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | FCLGA1567 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| TBTVersion | 1.0 |
| TCase | 70°C |
| ThreadCount | 16 |
| VTX | Yes |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/46494/intel-xeon-processor-l7555-24m-cache-1-86-ghz-5-86-gts-intel-qpi.html |