Intel Server CPU v7.2.6-L
Intel Xeon Processor E5-2418L
Benchmarks
Total score 1,192 / 10,000, rank 1840 of 2125.
Every score is out of 10,000, relative to the best CPUs. The total also counts the recommended price ($428, Intel ARK recommended customer price (2018)); see how scores work.
| Category | Score | Measured | |
|---|---|---|---|
| Single-thread | 1,601 | 977 points | |
| Multi-thread | 202 | 3,518 points | |
| 3D renderingestimated | 129 | ||
| Gamingestimated | 1,697 |
Sources: PassMark (Intel Xeon E5-2418L @ 2.00GHz, 1 samples)
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | Intel Xeon Processor E5-2418L |
| Processor number | E5-2418L |
| Codename | Sandy Bridge EN |
| Generation | Sandy Bridge |
| Microarchitecture | Sandy Bridge |
| Performance class | Xeon E5 |
| Segment | Embedded |
| Released | 2012-Q22012 |
| Status | Discontinued |
| Cores | 4 |
| Threads | 8 |
| Base clock | 2.00 GHz |
| Max clock | 2.10 GHz |
| Cache | 10 MB Intel Smart Cache |
| Bus | 6.4 GT/s |
| TDP | 50 W |
| Lithography (as published) | 32 nm |
| Max memory | 384 GB |
| Memory channels | 3 |
| PCIe revision | Gen 3.0 |
| PCIe lanes | 24 |
| Max CPUs per system | 2 |
| Socket | FCLGA1356LGA1356 |
| Memory | DDR3 800/1066/1333DDR3 |
| Recommended price | $428 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v14.0.0(32 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.1(SSE4.2) - simd: Intel SIMD
v2.0.0(AVX)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
- Foreshadow / L1 Terminal Fault (CVE-2018-3615, CVE-2018-3620, CVE-2018-3646): Speculative reads from the L1 data cache through non-present page table entries, breaking SGX, OS and VMM isolation.
- Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout) (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091): Data in store buffers, fill buffers and load ports leaks across privilege boundaries.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Server CPU v7.2.5 (Xeon E5-2407)
Performance
- ~Total score 1073 → 1192 (+11%)
- ~Single-thread 1391 → 1601 (+15%)
- ~Multi-thread 151 → 202 (+34%)
- ~3D rendering 94 → 129 (+37%)
- ~Gaming 1406 → 1697 (+21%)
Features
- +Hyper-Threading
- +Turbo Boost 2.0
- −Demand Based Switching
Specifications
- ~Threads: 4 → 8
- ~Base clock: 2.20 GHz → 2.00 GHz
- +Max clock: 2.10 GHz
- ~TDP: 80 W → 50 W
- ~PCIe revision: 3.0 → Gen 3.0
- ~Recommended price: $250 → $428
- −Instruction set: 64-bit
Since the previous minor (lower performance class): Intel Server CPU v7.1.0 (Pentium 1405)
Features
- +Hyper-Threading
- +Turbo Boost 2.0
- −vPro
- −Demand Based Switching
Specifications
- ~Cores: 2 → 4
- ~Threads: 2 → 8
- ~Base clock: 1.20 GHz → 2.00 GHz
- ~Max clock: 1.80 GHz → 2.10 GHz
- ~Cache: 5 MB Intel Smart Cache → 10 MB Intel Smart Cache
- ~Bus: 0 GT/s → 6.4 GT/s
- ~TDP: 40 W → 50 W
- ~Max memory: 375 GB → 384 GB
- ~Memory channels: 2 → 3
- ~PCIe revision: 3.0 → Gen 3.0
- ~Max CPUs per system: 1 → 2
- +Recommended price: $428
- −Instruction set: 64-bit
Since the previous major (previous generation): Intel Server CPU v6.2.6 (Xeon E7-4807)
Breaking changes
- ~Socket changed from LGA1567 to FCLGA1356
Components
Instruction sets
- +AVX
Features
- +Turbo Boost 2.0
Specifications
- ~Codename: Westmere EX → Sandy Bridge EN
- ~Microarchitecture: Westmere → Sandy Bridge
- ~Cores: 6 → 4
- ~Threads: 12 → 8
- ~Base clock: 1.86 GHz → 2.00 GHz
- +Max clock: 2.10 GHz
- ~Cache: 18 MB Intel Smart Cache → 10 MB Intel Smart Cache
- ~Bus: 4.8 GT/s → 6.4 GT/s
- ~TDP: 95 W → 50 W
- ~Max memory: 2 TB → 384 GB
- ~Memory channels: 4 → 3
- +PCIe revision: Gen 3.0
- +PCIe lanes: 24
- ~Max CPUs per system: 4 → 2
- ~Recommended price: $890 → $428
- −Instruction set: 64-bit
Raw source data
Show all 46 fields
| Field | Value |
|---|---|
| CpuId | 67026 |
| CpuName | Intel Xeon Processor E5-2418L |
| AESTech | Yes |
| BornOnDate | Q2'12 |
| Bus | 6.4 GT/s |
| BusNumPorts | 1 |
| Cache | 10 MB Intel Smart Cache |
| CertifiedUseConditions | Communications |
| ClockSpeed | 2.00 GHz |
| ClockSpeedMax | 2.10 GHz |
| CodeNameText | Products formerly Sandy Bridge EN |
| CoreCount | 4 |
| ECCMemory | Yes |
| EM64 | Yes |
| Embedded | Yes |
| ESUDate | Tuesday. June 30. 2020 |
| ExecuteDisable | Yes |
| ExpectedDiscontinuanceDate | Q2'19 |
| ExtendedPageTables | Yes |
| FlexMemoryTechnology | No |
| HyperThreading | Yes |
| IdentityProtectionTechVersion | No |
| Lithography | 32 nm |
| MarketSegment | Embedded |
| MaxCPUs | 2 |
| MaxMem | 384 GB |
| MaxTDP | 50 W |
| MemoryTypes | DDR3 800/1066/1333 |
| NumMemoryChannels | 3 |
| NumPCIExpressPorts | 24 |
| PCIExpressConfigs | Gen 3.0 |
| PCIExpressRevision | Gen 3.0 |
| ProcessorNumber | E5-2418L |
| ProductGroup | Intel Xeon Processor E5 Family |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | FCLGA1356 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| TBTVersion | 2.0 |
| TCase | 91°C |
| ThreadCount | 8 |
| TurboBoostTech2MaxFreq | 2.10 GHz |
| TXT | Yes |
| VTD | Yes |
| VTX | Yes |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/67026/intel-xeon-processor-e52418l-10m-2-0-ghz-6-4-gts-intel-qpi.html |