Intel CPU v5.1.1

Intel 486DX2

major
5
minor
1
patch
1
486DX2
suffix
—
No suffix

Metadata

PropertyValue
BrandIntel
Intel nameIntel 486DX2
Generationi486
Microarchitecturei486 (pipelined, on-die FPU)
Performance classDX
Released1992-031992
Data width32-bit
Address width32-bit
Base clock50 MHz
Max clock66 MHz
Cache8 KB L1
Transistors1,200,000
SocketSocket 3
Features
SourceCurated (historical-cpus.json)

Uses (dependencies)

Used by (0)

Nothing depends on this version.

Changelog

Since the previous patch: Intel CPU v5.1.0 (486DX)

Breaking changes

  • ~Socket changed from Socket 1 to Socket 3

Features

  • +Clock multiplier

Specifications

  • ~Base clock: 25 MHz → 50 MHz
  • ~Max clock: 50 MHz → 66 MHz

Since the previous minor (lower performance class): Intel CPU v5.0.0 (486SX)

Breaking changes

  • ~Socket changed from Socket 1 to Socket 3

Features

  • +On-die x87 FPU
  • +Clock multiplier

Specifications

  • ~Base clock: 16 MHz → 50 MHz
  • ~Max clock: 33 MHz → 66 MHz
  • ~Transistors: 1,185,000 → 1,200,000

Since the previous major (previous generation): Intel CPU v4.1.0 (386DX)

Features

  • +On-die L1 cache
  • +On-die x87 FPU
  • +Clock multiplier

Specifications

  • ~Microarchitecture: i386 (32-bit) → i486 (pipelined, on-die FPU)
  • ~Base clock: 12 MHz → 50 MHz
  • ~Max clock: 33 MHz → 66 MHz
  • +Cache: 8 KB L1
  • ~Transistors: 275,000 → 1,200,000
  • −Package: 132-pin PGA