Intel CPU v5.1.2
Intel 486DX4
Metadata
| Property | Value |
|---|---|
| Brand | Intel |
| Intel name | Intel 486DX4 |
| Generation | i486 |
| Microarchitecture | i486 (pipelined, on-die FPU) |
| Performance class | DX |
| Released | 1994-031994 |
| Data width | 32-bit |
| Address width | 32-bit |
| Base clock | 75 MHz |
| Max clock | 100 MHz |
| Cache | 16 KB L1 |
| Transistors | 1,600,000 |
| Socket | Socket 3 |
| Features | |
| Source | Curated (historical-cpus.json) |
Uses (dependencies)
- lithography: Intel Lithography
v6.0.0(600 nm BiCMOS)
Used by (0)
Nothing depends on this version.
Changelog
Since the previous patch: Intel CPU v5.1.1 (486DX2)
Specifications
- ~Base clock: 50 MHz → 75 MHz
- ~Max clock: 66 MHz → 100 MHz
- ~Cache: 8 KB L1 → 16 KB L1
- ~Transistors: 1,200,000 → 1,600,000
Since the previous minor (lower performance class): Intel CPU v5.0.0 (486SX)
Breaking changes
- ~Socket changed from Socket 1 to Socket 3
Features
- +On-die x87 FPU
- +Clock multiplier
Specifications
- ~Base clock: 16 MHz → 75 MHz
- ~Max clock: 33 MHz → 100 MHz
- ~Cache: 8 KB L1 → 16 KB L1
- ~Transistors: 1,185,000 → 1,600,000
Since the previous major (previous generation): Intel CPU v4.1.0 (386DX)
Features
- +On-die L1 cache
- +On-die x87 FPU
- +Clock multiplier
Specifications
- ~Microarchitecture: i386 (32-bit) → i486 (pipelined, on-die FPU)
- ~Base clock: 12 MHz → 75 MHz
- ~Max clock: 33 MHz → 100 MHz
- +Cache: 16 KB L1
- ~Transistors: 275,000 → 1,600,000
- −Package: 132-pin PGA