Intel Server CPU v3.2.0
Intel Xeon Processor E7210
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | Intel Xeon Processor E7210 |
| Processor number | E7210 |
| Codename | Tigerton |
| Generation | Core |
| Microarchitecture | Core |
| Performance class | Xeon 7000 series |
| Segment | Server |
| Released | 2007-Q32007 |
| Status | Discontinued |
| Cores | 2 |
| Base clock | 2.40 GHz |
| Cache | 8 MB L2 Cache |
| Bus | 1066 MHz |
| TDP | 80 W |
| Lithography (as published) | 65 nm |
| Transistors | 582 million |
| Die size | 286 mm2 |
| Instruction set | 64-bit |
| Socket | PPGA604PGA604 |
| Recommended price | $856 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v12.0.0(65 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.3.0(SSSE3)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous minor (lower performance class): Intel Server CPU v3.1.0 (Xeon LV 5128)
Breaking changes
- ~Socket changed from LGA771 to PPGA604
Features
- +Demand Based Switching
Specifications
- ~Codename: Woodcrest → Tigerton
- ~Base clock: 1.86 GHz → 2.40 GHz
- ~Cache: 4 MB L2 Cache → 8 MB L2 Cache
- ~TDP: 40 W → 80 W
- ~Transistors: 291 million → 582 million
- ~Die size: 143 mm2 → 286 mm2
- ~Recommended price: $412 → $856
Since the previous major (previous generation): Intel Server CPU v2.0.0 (Xeon LV 1.66 GHz, 2M Cache, 667 MHz FSB)
Breaking changes
- ~Socket changed from PPGA478 to PPGA604
Components
Instruction sets
- +SSSE3
Features
- +Intel 64
- +Demand Based Switching
- −EPT
- −Physical Address Extension
Specifications
- ~Codename: Sossaman → Tigerton
- ~Microarchitecture: Enhanced Pentium M → Core
- ~Base clock: 1.66 GHz → 2.40 GHz
- ~Cache: 2 MB L2 Cache → 8 MB L2 Cache
- ~Bus: 667 MHz → 1066 MHz
- ~TDP: 31 W → 80 W
- ~Transistors: 151 million → 582 million
- ~Die size: 90 mm2 → 286 mm2
- ~Instruction set: 32-bit → 64-bit
- +Recommended price: $856
Raw source data
Show all 36 fields
| Field | Value |
|---|---|
| CpuId | 30779 |
| CpuName | Intel Xeon Processor E7210 |
| BornOnDate | Q3'07 |
| Bus | 1066 MHz |
| Cache | 8 MB L2 Cache |
| ClockSpeed | 2.40 GHz |
| CodeNameText | Products formerly Tigerton |
| CoreCount | 2 |
| CoreVoltage | 1.0V-1.5V |
| DemandBasedSwitching | Yes |
| DieSize | 286 mm2 |
| EM64 | Yes |
| Embedded | No |
| ExecuteDisable | Yes |
| ExpectedDiscontinuanceDate | Q1'2010 |
| FSBParity | Yes |
| HaltState | Yes |
| HyperThreading | No |
| InstructionSet | 64-bit |
| Lithography | 65 nm |
| MarketSegment | Server |
| MaxTDP | 80 W |
| PackageSize | 53.3mm x 53.3mm |
| ProcessorNumber | E7210 |
| ProductGroup | Legacy Intel Xeon Processors |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | PPGA604 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| TBTVersion | No |
| TCase | 64°C |
| ThermalMonitoring2Indicator | Yes |
| TransistorCount | 582 million |
| TXT | No |
| VTX | Yes |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/30779/intel-xeon-processor-e7210-8m-cache-2-40-ghz-1066-mhz-fsb.html |