Intel SIMD v1.3.0

SSSE3

major
1
SSE
minor
3
SSSE3
patch
0
SSSE3
suffix
—
No suffix

Metadata

PropertyValue
NameSSSE3
Introduced2006
First implemented byCore 2 (Merom/Conroe)
Operations+ shuffle, absolute value, sign
SourceCurated (simd.json)

Uses (dependencies)

Used by (113)

Intel CPU (15)
Intel Mobile CPU (16)
Intel Low-power CPU (54)
Intel Server CPU (27)
Intel SIMD (1)

Changelog

Since the previous minor (lower performance class): Intel SIMD v1.2.0 (SSE3)

Specifications

  • ~First implemented by: Pentium 4 (Prescott) → Core 2 (Merom/Conroe)
  • ~Operations: + horizontal operations → + shuffle, absolute value, sign

Since the previous major (previous generation): Intel SIMD v0.0.1 (MMX)

Specifications

  • ~First implemented by: Pentium MMX (P55C) → Core 2 (Merom/Conroe)
  • ~Operations: packed integers → + shuffle, absolute value, sign
  • −Registers: 8 × 64-bit (aliased to x87)