Intel Server CPU v8.2.5
Intel Xeon Processor E7-4820 v2
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | Intel Xeon Processor E7-4820 v2 |
| Processor number | E7-4820V2 |
| Codename | Ivy Bridge |
| Generation | Ivy Bridge |
| Microarchitecture | Ivy Bridge |
| Performance class | Xeon E7 |
| Segment | Server |
| Released | 2014-Q12014 |
| Status | Discontinued |
| Cores | 8 |
| Threads | 16 |
| Base clock | 2.00 GHz |
| Max clock | 2.50 GHz |
| Cache | 16 MB |
| Bus | 7.2 GT/s |
| TDP | 105 W |
| Lithography (as published) | 22 nm |
| Max memory | 1.5 TB |
| Memory channels | 4 |
| PCIe revision | 3.0 |
| PCIe lanes | 32 |
| Max CPUs per system | 4 |
| Instruction set | 64-bit |
| Socket | FCLGA2011LGA2011 |
| Memory | DDR3 1066/1333/1600DDR3 |
| Recommended price | $1,446 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v15.0.0(22 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.1(SSE4.2) - simd: Intel SIMD
v2.0.0(AVX)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
- Foreshadow / L1 Terminal Fault (CVE-2018-3615, CVE-2018-3620, CVE-2018-3646): Speculative reads from the L1 data cache through non-present page table entries, breaking SGX, OS and VMM isolation.
- Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout) (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091): Data in store buffers, fill buffers and load ports leaks across privilege boundaries.
- Special Register Buffer Data Sampling (CrossTalk) (CVE-2020-0543): RDRAND/RDSEED results leak across cores through a shared staging buffer.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Server CPU v8.2.4 (Xeon E7-4809 v2)
Features
- +Turbo Boost 2.0
Specifications
- ~Cores: 6 → 8
- ~Threads: 12 → 16
- ~Base clock: 1.90 GHz → 2.00 GHz
- +Max clock: 2.50 GHz
- ~Cache: 12 MB → 16 MB
- ~Bus: 6.4 GT/s → 7.2 GT/s
- ~Recommended price: $1,223 → $1,446
Since the previous minor (lower performance class): Intel Server CPU v8.1.5 (Xeon E5-2407 v2)
Breaking changes
- ~Socket changed from FCLGA1356 to FCLGA2011
Security
- !Introduced: Special Register Buffer Data Sampling (CrossTalk)
Features
- +Hyper-Threading
- +Turbo Boost 2.0
- −Demand Based Switching
Specifications
- ~Codename: Ivy Bridge EN → Ivy Bridge
- ~Cores: 4 → 8
- ~Threads: 4 → 16
- ~Base clock: 2.40 GHz → 2.00 GHz
- ~Max clock: 2.40 GHz → 2.50 GHz
- ~Cache: 10 MB Intel Smart Cache → 16 MB
- ~Bus: 6.4 GT/s → 7.2 GT/s
- ~TDP: 80 W → 105 W
- ~Max memory: 384 GB → 1.5 TB
- ~Memory channels: 3 → 4
- ~PCIe lanes: 24 → 32
- ~Max CPUs per system: 2 → 4
- ~Recommended price: $250 → $1,446
Since the previous major (previous generation): Intel Server CPU v7.2.5 (Xeon E5-2407)
Breaking changes
- ~Socket changed from FCLGA1356 to FCLGA2011
Security
- !Introduced: Special Register Buffer Data Sampling (CrossTalk)
Features
- +Hyper-Threading
- +Secure Key (RDRAND)
- +Physical Address Extension
- +Turbo Boost 2.0
- −Demand Based Switching
Specifications
- ~Codename: Sandy Bridge EN → Ivy Bridge
- ~Microarchitecture: Sandy Bridge → Ivy Bridge
- ~Cores: 4 → 8
- ~Threads: 4 → 16
- ~Base clock: 2.20 GHz → 2.00 GHz
- +Max clock: 2.50 GHz
- ~Cache: 10 MB Intel Smart Cache → 16 MB
- ~Bus: 6.4 GT/s → 7.2 GT/s
- ~TDP: 80 W → 105 W
- ~Max memory: 384 GB → 1.5 TB
- ~Memory channels: 3 → 4
- ~PCIe lanes: 24 → 32
- ~Max CPUs per system: 2 → 4
- ~Recommended price: $250 → $1,446
Raw source data
Show all 56 fields
| Field | Value |
|---|---|
| CpuId | 75246 |
| CpuName | Intel Xeon Processor E7-4820 v2 |
| AdditionalInfoUrl | View now |
| AESTech | Yes |
| BornOnDate | Q1'14 |
| Bus | 7.2 GT/s |
| BusNumPorts | 3 |
| Cache | 16 MB |
| ClockSpeed | 2.00 GHz |
| ClockSpeedMax | 2.50 GHz |
| CodeNameText | Products formerly Ivy Bridge |
| CoreCount | 8 |
| ECCMemory | Yes |
| EM64 | Yes |
| Embedded | No |
| ESUDate | Tuesday. June 30. 2020 |
| ExecuteDisable | Yes |
| ExtendedPageTables | Yes |
| HaltState | Yes |
| HyperThreading | Yes |
| InstructionReplayTechVersion | No |
| InstructionSet | 64-bit |
| InstructionSetExtensions | Intel AVX |
| Lithography | 22 nm |
| MarketSegment | Server |
| MaxCPUs | 4 |
| MaxMem | 1.5 TB |
| MaxMemoryBandwidth | 68 GB/s |
| MaxTDP | 105 W |
| MemoryTypes | DDR3 1066/1333/1600 |
| NumMemoryChannels | 4 |
| NumPCIExpressPorts | 32 |
| OSGuardTechVersion | Yes |
| PackageSize | 52mm x 45mm |
| PCIExpressConfigs | x4. x8. x16 |
| PCIExpressRevision | 3.0 |
| PhysicalAddressExtension | 46-bit |
| ProcessorNumber | E7-4820V2 |
| ProductGroup | Intel Xeon Processor E7 v2 Family |
| ScalableSockets | S4S |
| SecureKeyTechVersion | Yes |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | FCLGA2011 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| SupplyStatus | Discontinued |
| TBTVersion | 2.0 |
| TCase | 68°C |
| ThermalMonitoring2Indicator | Yes |
| ThreadCount | 16 |
| TransactionalSynchronizationExtensionVersion | No |
| TurboBoostTech2MaxFreq | 2.50 GHz |
| TXT | Yes |
| VTD | Yes |
| VTX | Yes |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/75246/intel-xeon-processor-e74820-v2-16m-cache-2-00-ghz.html |