Intel SIMD v2.2.0

AVX-512

major
2
AVX
minor
2
AVX-512
patch
0
AVX-512
suffix
—
No suffix

Metadata

PropertyValue
NameAVX-512
Introduced2016
First implemented byXeon Phi (Knights Landing), Skylake-SP
Registers32 × 512-bit ZMM, 8 mask registers
Operations512-bit vectors, EVEX encoding
SourceCurated (simd.json)

Uses (dependencies)

Used by (462)

Intel CPU (19)
Intel Mobile CPU (33)
Intel HEDT CPU (18)
Intel Embedded CPU (10)
Intel Server CPU (369)
Intel Manycore CPU (11)
Intel SIMD (2)

Changelog

Since the previous minor (lower performance class): Intel SIMD v2.1.0 (AVX2)

Specifications

  • ~First implemented by: Haswell → Xeon Phi (Knights Landing), Skylake-SP
  • +Registers: 32 × 512-bit ZMM, 8 mask registers
  • ~Operations: + 256-bit integers, gather, FMA3 → 512-bit vectors, EVEX encoding

Since the previous major (previous generation): Intel SIMD v1.2.0 (SSE3)

Specifications

  • ~First implemented by: Pentium 4 (Prescott) → Xeon Phi (Knights Landing), Skylake-SP
  • +Registers: 32 × 512-bit ZMM, 8 mask registers
  • ~Operations: + horizontal operations → 512-bit vectors, EVEX encoding