Intel Low-power CPU v3.1.6
Intel Atom x3-C3405 Processor
Metadata
| Property | Value |
|---|---|
| Brand | Atom |
| Intel name | Intel Atom x3-C3405 Processor |
| Processor number | x3-C3405 |
| Codename | SoFIA LTE |
| Generation | Silvermont |
| Microarchitecture | Silvermont (out-of-order) |
| Performance class | Atom x3 |
| Segment | Mobile |
| Released | 2015-Q12015 |
| Status | Announced |
| Cores | 4 |
| Base clock | 1.20 GHz |
| Cache | 1 MB |
| Lithography (as published) | 28 nm |
| Max memory | 2 GB |
| Memory channels | 1 |
| Instruction set | 64-bit |
| Memory | 1x32 LPDDR2/3 1066LPDDR2 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v16.0.0(14 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.1(SSE4.2)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Low-power CPU v3.1.5-RK (Atom x3-C3295RK)
Specifications
- ~Codename: SoFIA 3G R → SoFIA LTE
- +Base clock: 1.20 GHz
- ~Cache: 1 MB L2 Cache → 1 MB
Since the previous minor (lower performance class): Intel Low-power CPU v3.0.6 (Atom C2516)
Breaking changes
- −Removed VT-x
Security
- ✓Fixed: Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout)
Features
- −VT-x
- −EPT
- −AES-NI
- −Execute Disable Bit
- −Physical Address Extension
- −ECC memory
- −QuickAssist
Specifications
- ~Codename: Rangeley → SoFIA LTE
- ~Base clock: 1.40 GHz → 1.20 GHz
- ~Cache: 2 MB → 1 MB
- ~Max memory: 32 GB → 2 GB
- ~Memory channels: 2 → 1
- +Instruction set: 64-bit
- −Threads: 4
- −TDP: 10 W
- −PCIe revision: 2
- −PCIe lanes: 8
- −Recommended price: $64
Since the previous major (previous generation): Intel Low-power CPU v2.0.6 (Atom S1240)
Breaking changes
- ~Memory changed from DDR3 to LPDDR2
- −Removed VT-x
Security
- !Introduced: Spectre variant 1 (bounds check bypass)
Components
Instruction sets
- +SSE4.1
- +SSE4.2
Features
- −Hyper-Threading
- −VT-x
- −ECC memory
Specifications
- ~Codename: Centerton → SoFIA LTE
- ~Microarchitecture: Saltwell (in-order) → Silvermont (out-of-order)
- ~Cores: 2 → 4
- ~Base clock: 1.60 GHz → 1.20 GHz
- ~Max memory: 8 GB → 2 GB
- −Threads: 4
- −TDP: 6.1 W
- −PCIe revision: 2.0
- −PCIe lanes: 8
- −Recommended price: $64
Raw source data
Show all 40 fields
| Field | Value |
|---|---|
| CpuId | 87530 |
| CpuName | Intel Atom x3-C3405 Processor |
| BasebandFunctions | n/a - WiFi only |
| BornOnDate | Q1'15 |
| BurstFrequency | 1.40 GHz |
| Cache | 1 MB |
| ClockSpeed | 1.20 GHz |
| CodeNameText | Products formerly SoFIA LTE |
| CoreCount | 4 |
| Embedded | No |
| GeneralPurposeIO | 5 x I2C |
| GraphicsDirectXSupport | 9.3 |
| GraphicsFreq | 456 MHz |
| GraphicsMaxResolutionIFP | 1280x800 |
| GraphicsOpenGLSupport | ES 3.0 |
| GraphicsOutput | MIPI DSI |
| InstructionSet | 64-bit |
| Lithography | 28 nm |
| MarketSegment | Mobile |
| MaxMem | 2 GB |
| MaxMemoryBandwidth | 4.2 GB/s |
| MemoryTypes | 1x32 LPDDR2/3 1066 |
| NumDisplaysSupported | 1 |
| NumMemoryChannels | 1 |
| NumUSBPorts | 1 |
| OperatingTemperature | -25°C to 85°C |
| OperatingTemperatureMax | 85 °C |
| OperatingTemperatureMin | -25 °C |
| PackageSize | 12mm x 12mm |
| ProcessorNumber | x3-C3405 |
| ProductGroup | Intel Atom Processor X Series |
| ProtocolStack | n/a - WiFi only |
| RadioFreqTransceiver | SMARTi 4.5s |
| RadioFreqTransceiverFunctions | clock |
| ScenarioDesignPower | 2 W |
| SecureBootTechVersion | Yes |
| StatusCodeText | Announced |
| UART | 7 x USIF configurable |
| USBRevision | 2.0 OTG |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/87530/intel-atom-x3c3405-processor-1m-cache-up-to-1-40-ghz.html |