Intel SIMD v1.0.0
SSE
major
1
SSE
minor
0
SSE
patch
0
SSE
suffix
—
No suffix
Metadata
| Property | Value |
|---|---|
| Name | SSE |
| Introduced | 1999 |
| First implemented by | Pentium III (Katmai) |
| Registers | 8 × 128-bit XMM |
| Operations | packed single-precision floats |
| Source | Curated (simd.json) |
Uses (dependencies)
- simd: Intel SIMD
v0.0.1(MMX)
Used by (19)
Intel CPU (14)
v7.0.1Celeron 300 MHz, 128K Cache, 66 MHz FSBv7.0.2Celeron 366 MHz, 128K Cache, 66 MHz FSBv7.0.3Celeron 433 MHz, 128K Cache, 66 MHz FSBv7.0.4Celeron 566 MHz, 128K Cache, 66 MHz FSBv7.0.5Celeron 733 MHz, 128K Cache, 66 MHz FSBv7.0.6Celeron 850 MHz, 128K Cache, 100 MHz FSBv7.1.0Pentium Prov7.1.3Pentium III (Katmai)v7.1.4Pentium III 600 MHz, 256K Cache, 100 MHz FSBv7.1.5Pentium III 700 MHz, 256K Cache, 100 MHz FSBv7.1.6Pentium III 733 MHz, 256K Cache, 133 MHz FSBv7.1.7Pentium III 850 MHz, 256K Cache, 100 MHz FSBv7.1.8Pentium III 866 MHz, 256K Cache, 133 MHz FSBv7.1.9Pentium III 1.00 GHz, 256K Cache, 100 MHz FSB
Intel Mobile CPU (1)
v0.0.1Mobile Celeron LV 650 MHz, 256K Cache, 100 MHz FSB
Intel Server CPU (3)
Intel SIMD (1)
v1.1.0SSE2
Changelog
Since the previous major (previous generation): Intel SIMD v0.0.1 (MMX)
Components
Specifications
- ~First implemented by: Pentium MMX (P55C) → Pentium III (Katmai)
- ~Registers: 8 × 64-bit (aliased to x87) → 8 × 128-bit XMM
- ~Operations: packed integers → packed single-precision floats